Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/06/2024
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Application #:
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17165797
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Filing Dt:
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02/02/2021
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Publication #:
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Pub Dt:
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05/27/2021
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Inventor:
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Cheng-Jer YANG
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Title:
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THROUGH-SILICON VIA (TSV) FAULT-TOLERANT CIRCUIT, METHOD FOR TSV FAULT-TOLERANCE AND INTEGRATED CIRCUIT (IC)
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NO. 388, XINGYE AVENUE |
ECONOMIC AND TECHNOLOGICAL DEVELOPMENT AREA |
HEFEI, ANHUI, CHINA |
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SHEPPARD MULLIN RICHTER & HAMPTON LLP |
379 LYTTON AVE. |
ATTN: JING ZHENG |
PALO ALTO, CA 94301 |
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06/23/2024 06:44 AM
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