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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
03/28/2023
Application #:
17481341
Filing Dt:
09/22/2021
Publication #:
Pub Dt:
05/19/2022
Inventors:
Chih-Wei LAI, Yi-Han WU, Hsin-Kun HSU, Yun-Jen TING, Kun-Hsin LIN
Title:
INTEGRATED CIRCUIT WITH CAPABILITY OF INHIBITING ESD ZAP
Assignment: 1
Reel/Frame:
057553/0059Recorded: 09/22/2021Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
09/22/2021
Exec Dt:
09/17/2021
Exec Dt:
09/22/2021
Exec Dt:
09/22/2021
Exec Dt:
09/22/2021
Assignee:
ROOM 305, NO.47, PARK AVENUE II RD., HSINCHU SCIENCE PARK
HSIN-CHU, TAIWAN 300091
Correspondent:
WPAT, PC INTELLECTUAL PROPERTY ATTORNEYS
8230 BOONE BLVD, SUITE 405
VIENNA, VA 22182

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