Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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17831019
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Filing Dt:
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06/02/2022
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Publication #:
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Pub Dt:
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01/05/2023
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Inventors:
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Jaeduk HAN, Youngbog YOON
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Title:
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METHOD FOR GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2091, GYEONGCHUNG-DAERO, BUBAL-EUP |
| ICHEON, KOREA, REPUBLIC OF 17336 |
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| 222, WANGSIMNI-RO, |
| SEONGDONG-GU, |
| SEOUL, KOREA, REPUBLIC OF 04763 |
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| AMPACC LAW GROUP, PLCC |
| 6100 219TH ST SW #580 |
| MOUNTLAKE TERRACE, WA 98043 |
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06/25/2024 03:41 PM
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