Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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08/20/2024
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Application #:
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17815807
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Filing Dt:
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07/28/2022
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Publication #:
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Pub Dt:
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03/02/2023
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Inventors:
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Vivek Mohan Sharma, Roberto Colombo
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Title:
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PROCESSING SYSTEM ERROR MANAGEMENT, RELATED INTEGRATED CIRCUIT, APPARATUS AND METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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BAHNHOFSTRASSE 18 |
ASCHHEIM-DORNACH, GERMANY 85609 |
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SLATER MATSIL, LLP C/O STMICROELECTRONICS |
17950 PRESTON RD. |
SUITE 1000 |
DALLAS, TX 75252 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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39, CHEMIN DU CHAMP-DES-FILLES |
PLAN-LES-OUATES |
GENEVA, SWITZERLAND 1228 |
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SLATER MATSIL, LLP C/O STMICROELECTRONICS |
17950 PRESTON RD. |
SUITE 1000 |
DALLAS, TX 75252 |
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09/23/2024 01:01 AM
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