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Patent Assignment Details
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Reel/Frame:005066/0653   Pages: 1
Recorded: 04/24/1989
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST.
Total properties: 1
1
Patent #:
Issue Dt:
12/11/1990
Application #:
07303845
Filing Dt:
01/30/1989
Title:
A SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MOS TRANSISTOR WITH A THRESHOLD LEVEL TO ENABLE A LEVEL CONVERSION
Assignor
1
Exec Dt:
03/31/1989
Assignee
1
33-1, SHIBA 5-CHOME, MINATO-KU
TOKYO, JAPAN
Correspondence name and address
J. WARREN WHITESEL
LAFF, WHITESEL, CONTE & SARET
401 NORTH MICHIGAN AVE.
CHICAGO, IL 60611

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