Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 009869/0842 | |
| Pages: | 5 |
| | Recorded: | 03/30/1999 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09281729
|
Filing Dt:
|
03/30/1999
|
|
Title:
|
LOW COST SILICON SUBSTRATE WITH IMPURITY GETTERING AND LATCH UP PROTECTION AND METHOD OF MANUFACTURE
|
|
|
Assignee
|
|
|
|
|
| 4111 N.E. 112TH AVENUE |
| VANCOUVER, WASHINGTON 98682 |
|
|
Correspondence name and address
|
| |
KOLISCH, HARTWELL, DICKINSON, ET AL
|
| |
DAVID A. FANNING
|
| |
200 PACIFIC BUILDING
|
| |
520 S.W. YAMHILL STREET
|
| |
PORTLAND, OREGON 97204
|
Search Results as of:
05/17/2024 10:55 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
