Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 011404/0417 | |
| Pages: | 5 |
| | Recorded: | 12/18/2000 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09739732
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Filing Dt:
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12/18/2000
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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METHOD OF FABRICATING POWER VLSI DIODE DEVICES
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Assignees
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| 2372-C QUME DRIVE |
| SAN JOSE, CALIFORNIA 95131 |
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| 1-6 MATSUSAKADAIRA TAIWA-CHO |
| KUROKAWA-GUN, MIYAGI 981-3493, JAPAN |
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Correspondence name and address
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MYERS, DAWES & ANDRAS LLP
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DAVID L. HENTY
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650 TOWN CENTER DRIVE, SUITE 650
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COSTA MESA, CA 92626
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