Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 011653/0786 | |
| Pages: | 6 |
| | Recorded: | 03/26/2001 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2002
|
Application #:
|
09595143
|
Filing Dt:
|
06/16/2000
|
Title:
|
Architecture for high speed memory circuit having a relatively large number of internal data lines
|
|
Assignees
|
|
|
4815 LIST DRIVE, SUITE 109 |
COLORADO SPRINGS, COLORADO 80919 |
|
|
|
6-7-35 KITA-SHINAGAWA SHINAGAWA-KU |
TOKYO, JAPAN 141-0 |
|
Correspondence name and address
|
|
COOK, ALEX ET AL
|
|
MICHAEL J MCGEE
|
|
200 W. ADAMS
|
|
CHICAGO, IL 60606
|
Search Results as of:
05/14/2024 10:10 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|