Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 011967/0430 | |
| Pages: | 3 |
| | Recorded: | 03/27/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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03/18/1997
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Application #:
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08185153
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Filing Dt:
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01/24/1994
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Title:
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LOGIC SIMULATOR
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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08379769
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Filing Dt:
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01/27/1995
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Title:
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APPARATUS FOR PERFORMING LOGIC SIMULATION
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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08789544
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Filing Dt:
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01/27/1997
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Title:
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APPARATUS AND METHOD OF SIMULTANEOUSLY READING AND WRITING DATA IN A SEMICONDUCTOR DEVICE HAVING A PLURALITY OF FLASH MEMORIES
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08796751
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Filing Dt:
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02/06/1997
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Title:
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MEMORY APPARATUS AND MEMORY CONTROL METHOD
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09051094
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Filing Dt:
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04/14/1998
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING ERROR DETECTION AND CORRECTION
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Assignee
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| TSUZUKI-KU, YOKOHAMA CITY |
| 1 HIGASHIKATA-CHO |
| KANAGAWA 224-0045, JAPAN |
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Correspondence name and address
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OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT
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MARVIN J. SPIVAK
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FOURTH FLOOR
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1755 JEFFERSON DAVIS HIGHWAY
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ARLINGTON, VA 22202
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