Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 013650/0010 | |
| Pages: | 10 |
| | Recorded: | 05/13/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09705880
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Filing Dt:
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11/06/2000
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Title:
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METHOD OF FORMING A HIGHLY INTEGRATED NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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09797990
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Filing Dt:
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03/05/2001
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Publication #:
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Pub Dt:
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11/01/2001
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Title:
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PHASE LOCKED LOOP CIRCUIT AND METHOD OF FREQUENCY MODULATION IN PHASE LOCKED LOOP CIRCUIT
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09932875
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Filing Dt:
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08/21/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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METHOD OF TRANSCRIBING A WIRING PATTERN FROM AN ORIGINAL SUBSTRATE TO A SUBSTRATE WITH CLOSELY MATCHED THERMAL EXPANSION COEFFICIENTS BETWEEN BOTH SUBSTRATES FOR DIMENSIONAL CONTROL OF THE TRANSCRIBED PATTERN
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10197670
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Filing Dt:
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07/18/2002
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
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Assignee
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| 1753 SHIMONUMABE |
| NAKAHARA-KU, KAWASAKI |
| KANAGAWA 211-8668, JAPAN |
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Correspondence name and address
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YOUNG & THOMPSON
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ROLAND E. LONG, JR.
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SECOND FLOOR
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745 SOUTH 23RD STREET
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ARLINGTON, VA 22202
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