Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 013762/0566 | |
| Pages: | 4 |
| | Recorded: | 02/19/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10261904
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Filing Dt:
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10/01/2002
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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FRACTIONAL N FREQUENCY SYNTHESIZER
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10262095
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Filing Dt:
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10/01/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10278567
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Filing Dt:
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10/23/2002
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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Synchronous DRAM controller and control method for the same
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10282500
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Filing Dt:
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10/29/2002
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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INTERNAL VOLTAGE STEP-DOWN CIRCUIT
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10299611
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Filing Dt:
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11/19/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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DISPLAY CONTROL CIRCUIT AND DISPLAY DEVICE
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10301240
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Filing Dt:
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11/21/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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USB-HUB DEVICE AND ITS CONTROL METHOD
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10306314
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Filing Dt:
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11/27/2002
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Publication #:
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Pub Dt:
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05/29/2003
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Title:
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CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA 211-8668, JAPAN |
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Correspondence name and address
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DARRYL G. WALKER
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300 S. FIRST STREET
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SUITE 235
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SAN JOSE, CA 95113
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