Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 015368/0427 | |
| Pages: | 5 |
| | Recorded: | 05/28/2004 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09850254
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Filing Dt:
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05/07/2001
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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SEMICONDUCTOR APPARATUS INCLUDING A MULTI-LAYER WIRING CONFIGURATION AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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09873470
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Filing Dt:
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06/04/2001
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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SEMICONDUCTOR APPARATUS
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09947737
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Filing Dt:
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09/06/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09964995
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Filing Dt:
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09/27/2001
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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Semiconductor device and manufacturing method therefor
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09981402
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Filing Dt:
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10/17/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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Semiconductor device and method for its manufacture
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10287238
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Filing Dt:
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11/04/2002
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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Semiconductor device
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10618508
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Filing Dt:
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07/11/2003
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10665639
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Filing Dt:
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09/18/2003
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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Semiconductor device including an insulated gate field effect transistor and method of manufacting the same
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Assignee
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2-1, YAESU 2-CHOME, CHUO-KU |
TOKYO, JAPAN |
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Correspondence name and address
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DARRYL G. WALKER
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300 S. FIRST STREET
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SUITE 235
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SAN JOSE, CA 95113
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