Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 018440/0157 | |
| Pages: | 8 |
| | Recorded: | 10/12/2006 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10558269
|
Filing Dt:
|
10/12/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
Stackable Semiconductor Chip, Stacked Semiconductor Chip Module, and Assembling, Identification and Module Environment Setting Methods Therefor
|
|
Assignees
|
|
|
22-22, NAGAIKE-CHO, ABENO-KU, OSAKA-SHI |
OSAKA, JAPAN 545-8522 |
|
|
|
4-1, MARUNOUCHI 2-CHOME, CHIYODA-KU |
TOKYO, JAPAN 100-6334 |
|
|
|
1-1, SHIBAURA 1-CHOME |
CHIYODA-KU, TOKYO, JAPAN 100-6334 |
|
Correspondence name and address
|
|
H. WARREN BURNAM, JR.
|
|
NIXON & VANDERHYE P.C.
|
|
901 NORTH GLEBE ROAD
|
|
11TH FLOOR
|
|
ARLINGTON, VA 22203
|
Search Results as of:
05/13/2024 06:19 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|