Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 019118/0179 | |
| Pages: | 2 |
| | Recorded: | 03/21/2007 | | |
| Attorney Dkt #: | HEIWA.036AUS |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11663526
|
Filing Dt:
|
03/21/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit
|
|
|
Assignee
|
|
|
|
|
| 32-1, ASAHICHO 1-CHOME, NERIMA-KU |
| TOKYO, 179-0071, JAPAN |
|
|
Correspondence name and address
|
| |
YASUO MURAMATSU
|
| |
MURAMATSU & ASSOCIATES
|
| |
SUITE 310
|
| |
114 PACIFICA
|
| |
IRVINE, CA 92618
|
Search Results as of:
05/04/2024 11:01 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
