Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 019353/0699 | |
| Pages: | 3 |
| | Recorded: | 05/30/2007 | | |
| Attorney Dkt #: | 1374.36694CV6 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09208019
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Filing Dt:
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12/09/1998
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DEPOSITED LAYER FOR GATE INSULATION
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09961301
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Filing Dt:
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09/25/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING FLOATING GATE AND DEPOSITED FILM
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09961360
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Filing Dt:
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09/25/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND HAVING DEPOSITED LAYER FOR GATE INSULATION
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10635511
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Filing Dt:
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08/07/2003
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DEPOSITED LAYER FOR GATE INSULATION
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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11178375
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Filing Dt:
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07/12/2005
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Publication #:
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Pub Dt:
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11/03/2005
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DEPOSITED LAYER FOR GATE INSULATION
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11505296
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Filing Dt:
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08/17/2006
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DEPOSITED LAYER FOR GATE INSULATION
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Assignee
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| 6-2, OTEMACHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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ANTONELLI, TERRY, STOUT & KRAUS, LLP
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1300 NORTH 17TH STREET - SUITE 1800
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ARLINGTON, VA 22209
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