Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 019795/0655 | |
| Pages: | 3 |
| | Recorded: | 09/10/2007 | | |
Attorney Dkt #: | SLA0953 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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10971204
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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CROSS-POINT RESISTOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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10976594
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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ALD ZNO SEED LAYER FOR DEPOSITION OF ZNO NANOSTRUCTURES ON A SILICON SUBSTRATE
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Patent #:
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Issue Dt:
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03/20/2007
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Application #:
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10985462
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Filing Dt:
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11/09/2004
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Publication #:
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Pub Dt:
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05/12/2005
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Title:
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SACRIFICIAL SHALLOW TRENCH ISOLATION OXIDE LINER FOR STRAINED-SILICON CHANNEL CMOS DEVICES
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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11046411
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Filing Dt:
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01/28/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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STRAINED SILICON DEVICES TRANSFER TO GLASS FOR DISPLAY APPLICATIONS
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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11416983
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Filing Dt:
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05/02/2006
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Title:
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STEP-OVER LITHOGRAPHY TO PRODUCE PARABOLIC PHOTORESIST PROFILES FOR MICROLENS FORMATION
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Assignee
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22-22, NAGAIKE-CHO, ABENO-KU |
OSAKA, JAPAN 545-8522 |
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Correspondence name and address
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THERESA BELLAND
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5750 NW PACIFIC RIM BLVD
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CAMAS, WA 98607
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