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Patent Assignment Details
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Reel/Frame:019795/0655   Pages: 3
Recorded: 09/10/2007
Attorney Dkt #:SLA0953
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 5
1
Patent #:
Issue Dt:
03/20/2007
Application #:
10971204
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
04/21/2005
Title:
CROSS-POINT RESISTOR MEMORY ARRAY
2
Patent #:
Issue Dt:
03/20/2007
Application #:
10976594
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/04/2006
Title:
ALD ZNO SEED LAYER FOR DEPOSITION OF ZNO NANOSTRUCTURES ON A SILICON SUBSTRATE
3
Patent #:
Issue Dt:
03/20/2007
Application #:
10985462
Filing Dt:
11/09/2004
Publication #:
Pub Dt:
05/12/2005
Title:
SACRIFICIAL SHALLOW TRENCH ISOLATION OXIDE LINER FOR STRAINED-SILICON CHANNEL CMOS DEVICES
4
Patent #:
Issue Dt:
02/13/2007
Application #:
11046411
Filing Dt:
01/28/2005
Publication #:
Pub Dt:
08/03/2006
Title:
STRAINED SILICON DEVICES TRANSFER TO GLASS FOR DISPLAY APPLICATIONS
5
Patent #:
Issue Dt:
03/13/2007
Application #:
11416983
Filing Dt:
05/02/2006
Title:
STEP-OVER LITHOGRAPHY TO PRODUCE PARABOLIC PHOTORESIST PROFILES FOR MICROLENS FORMATION
Assignor
1
Exec Dt:
09/10/2007
Assignee
1
22-22, NAGAIKE-CHO, ABENO-KU
OSAKA, JAPAN 545-8522
Correspondence name and address
THERESA BELLAND
5750 NW PACIFIC RIM BLVD
CAMAS, WA 98607

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