Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 020573/0634 | |
| Pages: | 3 |
| | Recorded: | 02/19/2008 | | |
| Attorney Dkt #: | 029471-0243 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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12071221
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Filing Dt:
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02/19/2008
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Publication #:
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Pub Dt:
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08/21/2008
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Title:
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Array-type processor having delay adjusting circuit for adjusting a clock cycle in accordance with a critical path delay of the data path
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA, JAPAN 211-8668 |
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Correspondence name and address
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GEORGE C. BECK
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FOLEY & LARDNER LLP
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WASHINGTON HARBOUR
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3000 K STREET NW, SUITE 500
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WASHINGTON, D.C. 20007-5143
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