Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021277/0720 | |
| Pages: | 3 |
| | Recorded: | 07/15/2008 | | |
| Attorney Dkt #: | 016891-0929 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12219021
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Filing Dt:
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07/15/2008
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA, JAPAN 211-8668 |
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Correspondence name and address
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GEORGE C. BECK
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FOEY & LARDNER LLP
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WASHINGTON HARBOUR
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3000 K STREET NW, SUITE 500
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WASHINGOTN, DC 20007-5143
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