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Reel/Frame:022343/0219   Pages: 37
Recorded: 03/04/2009
Attorney Dkt #:3222.194STR0 (EXHIBIT 1)
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 22
1
Patent #:
5493687
Issue Dt:
02/20/1996
Application #:
07726773
Filing Dt:
07/08/1991
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
2
Patent #:
5438668
Issue Dt:
08/01/1995
Application #:
07857599
Filing Dt:
03/31/1992
Title:
A SYSTEM AND METHOD FOR EXTRACTION, ALIGNMENT AND DECODING OF CISC INSTRUCTIONS INTO A NANO-INSTRUCTION BUCKET FOR EXECUTION BY A RISC COMPUTER
3
Patent #:
5497499
Issue Dt:
03/05/1996
Application #:
08219425
Filing Dt:
03/29/1994
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
4
Patent #:
5546552
Issue Dt:
08/13/1996
Application #:
08440225
Filing Dt:
05/12/1995
Title:
METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS AND COMBINING THEM INTO A FINAL BUCKET FOR PROCESSING ON A HOST PROCESSOR
5
Patent #:
5619666
Issue Dt:
04/08/1997
Application #:
08460272
Filing Dt:
06/02/1995
Title:
SYSTEM FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS AND COMBINING THEM INTO A FINAL BUCKET FOR PROCESSING ON A HOST PROCESSOR
6
Patent #:
5560035
Issue Dt:
09/24/1996
Application #:
08465239
Filing Dt:
06/05/1995
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
7
Patent #:
5737624
Issue Dt:
04/07/1998
Application #:
08594401
Filing Dt:
01/31/1996
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
8
Patent #:
5682546
Issue Dt:
10/28/1997
Application #:
08665845
Filing Dt:
06/19/1996
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
9
Patent #:
5983334
Issue Dt:
11/09/1999
Application #:
08784339
Filing Dt:
01/16/1997
Title:
SUPERSCALAR MICROPROCESSOR FOR OUT-OF-ORDER AND CONCURRENTLY EXECUTING AT LEAST TWO RISC INSTRUCTIONS TRANSLATING FROM IN-ORDER CISC INSTRUCTIONS
10
Patent #:
5838986
Issue Dt:
11/17/1998
Application #:
08937361
Filing Dt:
09/25/1997
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
11
Patent #:
5974526
Issue Dt:
10/26/1999
Application #:
08990414
Filing Dt:
12/15/1997
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
12
Patent #:
6044449
Issue Dt:
03/28/2000
Application #:
09188708
Filing Dt:
11/10/1998
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
13
Patent #:
6289433
Issue Dt:
09/11/2001
Application #:
09329354
Filing Dt:
06/10/1999
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
14
Patent #:
6263423
Issue Dt:
07/17/2001
Application #:
09401860
Filing Dt:
09/22/1999
Title:
SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTION TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
15
Patent #:
6249856
Issue Dt:
06/19/2001
Application #:
09480136
Filing Dt:
01/10/2000
Title:
RISC microprocessor architecture implementing multiple typed register sets
16
Patent #:
7555631
Issue Dt:
06/30/2009
Application #:
10060086
Filing Dt:
01/31/2002
Publication #:
US20030115440
Pub Dt:
06/19/2003
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
17
Patent #:
6954847
Issue Dt:
10/11/2005
Application #:
10061295
Filing Dt:
02/04/2002
Publication #:
US20030084270
Pub Dt:
05/01/2003
Title:
SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
18
Patent #:
7051187
Issue Dt:
05/23/2006
Application #:
10086197
Filing Dt:
03/01/2002
Publication #:
US20030005260
Pub Dt:
01/02/2003
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
19
Patent #:
7343473
Issue Dt:
03/11/2008
Application #:
11167289
Filing Dt:
06/28/2005
Publication #:
US20050251653
Pub Dt:
11/10/2005
Title:
SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
20
Patent #:
7685402
Issue Dt:
03/23/2010
Application #:
11651009
Filing Dt:
01/09/2007
Publication #:
US20070113047
Pub Dt:
05/17/2007
Title:
RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS
21
Patent #:
7802074
Issue Dt:
09/21/2010
Application #:
11730566
Filing Dt:
04/02/2007
Publication #:
US20080059770
Pub Dt:
03/06/2008
Title:
SUPERSCALAR RISC INSTRUCTION SCHEDULING
22
Patent #:
7664935
Issue Dt:
02/16/2010
Application #:
12046318
Filing Dt:
03/11/2008
Publication #:
US20080162880
Pub Dt:
07/03/2008
Title:
SYSTEM AND METHOD FOR TRANSLATING NON-NATIVE INSTRUCTIONS TO NATIVE INSTRUCTIONS FOR PROCESSING ON A HOST PROCESSOR
Assignor
1
TRANSMETA LLC
Exec Dt:
01/28/2009
Assignee
1
INTELLECTUAL VENTURE FUNDING LLC
502 E. JOHN STREET
CARSON CITY, NEVADA 89706
Correspondence name and address
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

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