Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024294/0032 | |
| Pages: | 8 |
| | Recorded: | 04/27/2010 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09420535
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Filing Dt:
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10/19/1999
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Title:
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OTP SECTOR DOUBLE PROTECTION FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10899684
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Filing Dt:
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07/26/2004
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Title:
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METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11546688
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Filing Dt:
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10/12/2006
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Publication #:
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Pub Dt:
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02/08/2007
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Title:
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Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices
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Patent #:
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Issue Dt:
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08/13/2013
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Application #:
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12187276
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Filing Dt:
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08/06/2008
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
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Assignee
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| 915 DEGUIGNE DRIVE |
| M/S 250 |
| SUNNYVALE, CALIFORNIA 94088 |
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Correspondence name and address
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PETER Y. WANG
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915 DEGUIGNE DRIVE
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M/S 250
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SUNNYVALE, CA 94088
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