Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024300/0850 | |
| Pages: | 8 |
| | Recorded: | 04/28/2010 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10762071
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Filing Dt:
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01/20/2004
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Title:
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METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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10799413
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Filing Dt:
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03/12/2004
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Title:
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AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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10823970
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Filing Dt:
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04/13/2004
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Title:
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SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10838962
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Filing Dt:
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05/04/2004
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Title:
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METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10859369
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Filing Dt:
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06/01/2004
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Title:
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METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10861575
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Filing Dt:
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06/04/2004
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Title:
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METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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10896292
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Filing Dt:
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07/20/2004
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Title:
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APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10917562
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Filing Dt:
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08/13/2004
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Title:
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USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
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Assignee
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| 915 DEGUIGNE DRIVE |
| M/S 250 |
| SUNNYVALE, CALIFORNIA 94088 |
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Correspondence name and address
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PETER Y. WANG
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915 DEGUIGNE DRIVE
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M/S 250
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SUNNYVALE, CA 94088
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