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Patent Assignment Details
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Reel/Frame:031543/0254   Pages: 3
Recorded: 11/05/2013
Attorney Dkt #:EPLIDA 93P00002
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14
1
Patent #:
Issue Dt:
05/28/1996
Application #:
08374990
Filing Dt:
01/19/1995
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
2
Patent #:
Issue Dt:
02/25/1997
Application #:
08620686
Filing Dt:
03/21/1996
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
3
Patent #:
Issue Dt:
10/20/1998
Application #:
08797051
Filing Dt:
02/10/1997
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
4
Patent #:
Issue Dt:
11/28/2000
Application #:
09141563
Filing Dt:
08/28/1998
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
5
Patent #:
Issue Dt:
07/31/2001
Application #:
09573609
Filing Dt:
05/19/2000
Title:
Semiconductor integrated circuits with power reduction mechanism
6
Patent #:
Issue Dt:
05/07/2002
Application #:
09832853
Filing Dt:
04/12/2001
Publication #:
Pub Dt:
05/09/2002
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
7
Patent #:
Issue Dt:
09/16/2003
Application #:
10103966
Filing Dt:
03/25/2002
Publication #:
Pub Dt:
09/26/2002
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
8
Patent #:
Issue Dt:
01/04/2005
Application #:
10626532
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
08/12/2004
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
9
Patent #:
Issue Dt:
04/04/2006
Application #:
11004823
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
10
Patent #:
Issue Dt:
05/08/2007
Application #:
11356100
Filing Dt:
02/17/2006
Publication #:
Pub Dt:
06/29/2006
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
11
Patent #:
Issue Dt:
07/10/2007
Application #:
11599275
Filing Dt:
11/15/2006
Publication #:
Pub Dt:
03/15/2007
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
12
Patent #:
Issue Dt:
06/17/2008
Application #:
11768981
Filing Dt:
06/27/2007
Publication #:
Pub Dt:
10/25/2007
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
13
Patent #:
Issue Dt:
02/23/2010
Application #:
12133969
Filing Dt:
06/05/2008
Publication #:
Pub Dt:
12/18/2008
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
14
Patent #:
Issue Dt:
01/31/2012
Application #:
12645784
Filing Dt:
12/23/2009
Publication #:
Pub Dt:
05/06/2010
Title:
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM
Assignors
1
Exec Dt:
12/21/1993
2
Exec Dt:
12/21/1993
3
Exec Dt:
12/21/1993
Assignee
1
6, KANDA SURUGADAI 4-CHOME
CHIYODA-KU
TOKYO, JAPAN
Correspondence name and address
MOSAID CORPORATION LTD.
5700 GRANITE PARKWAY
SUITE 960
PLANO, TX 75024

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