Patent Assignment Details
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| Reel/Frame: | 032005/0691 | |
| Pages: | 2 |
| | Recorded: | 01/21/2014 | | |
| Attorney Dkt #: | P605790-01 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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13743073
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Filing Dt:
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01/16/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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MEMORY CONTROLLER AND MEMORY ACCESS SYSTEM WITH ERROR DETECTION USING DATA COMPARISON OF LOOP-BACKED SIGNALS
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Assignee
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| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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PANASONIC CORPORATION
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2-1-61, SHIROMI, CHUO-KU
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7F OBP PANASONIC TOWER
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OSAKA, 540-6207 JAPAN
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