Total properties:
68
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12501435
|
Filing Dt:
|
07/12/2009
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
SENSE AMPLIFIER USED IN ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND THE IMPLEMENTING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
12505591
|
Filing Dt:
|
07/20/2009
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
DECODING CIRCUIT WITHSTANDING HIGH VOLTAGE VIA LOW-VOLTAGE MOS TRANSISTOR AND THE IMPLEMENTING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
12505599
|
Filing Dt:
|
07/20/2009
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
SELF-CALIBRATION METHOD OF A READING CIRCUIT OF A NONVOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12832963
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/13/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH ALTERNATELY ARRANGED P-TYPE AND N-TYPE THIN SEMICONDUCTOR LAYERS AND METHOD FOR MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12958080
|
Filing Dt:
|
12/01/2010
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
STACK INDUCTOR WITH DIFFERENT METAL THICKNESS AND METAL WIDTH
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12963242
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12963462
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
STACKED INDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
12966078
|
Filing Dt:
|
12/13/2010
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
High Voltage Bipolar Transistor with Pseudo Buried Layers
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12971063
|
Filing Dt:
|
12/17/2010
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
SIGE HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12975545
|
Filing Dt:
|
12/22/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
Parasitic Vertical PNP Bipolar Transistor And Its Fabrication Method In Bicmos Process
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12978552
|
Filing Dt:
|
12/25/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
PARASITIC VERTICAL PNP BIPOLAR TRANSISTOR IN BICMOS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12979907
|
Filing Dt:
|
12/28/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
NOVEL MANUFACTURING APPROACH FOR COLLECTOR AND A BURIED LAYER OF BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12979999
|
Filing Dt:
|
12/28/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
A Novel Manufacturing Approach for Collector and A Buried Layer Of Bipolar Transistor
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13075017
|
Filing Dt:
|
03/29/2011
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
METHOD OF MANUFACTURING SUPERJUNCTION STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13076289
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
TERMINAL STRUCTURE FOR SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
13156286
|
Filing Dt:
|
06/08/2011
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
METHOD FOR ETCHING AND FILLING DEEP TRENCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13167450
|
Filing Dt:
|
06/23/2011
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
METHOD FOR MANUFACTURING TRENCH TYPE SUPERJUNCTION DEVICE AND TRENCH TYPE SUPERJUNCTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13218316
|
Filing Dt:
|
08/25/2011
|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
Title:
|
PARASITIC PIN DEVICE IN A BICMOS PROCESS AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13220485
|
Filing Dt:
|
08/29/2011
|
Publication #:
|
|
Pub Dt:
|
03/01/2012
| | | | |
Title:
|
VERTICAL PARASITIC PNP DEVICE IN A BICMOS PROCESS AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13227387
|
Filing Dt:
|
09/07/2011
|
Publication #:
|
|
Pub Dt:
|
03/08/2012
| | | | |
Title:
|
PSEUDO BURIED LAYER AND MANUFACTURING METHOD OF THE SAME, DEEP HOLE CONTACT AND BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13228305
|
Filing Dt:
|
09/08/2011
|
Publication #:
|
|
Pub Dt:
|
03/15/2012
| | | | |
Title:
|
PARASITIC PNP BIPOLAR TRANSISTOR IN A SILICON-GERMANIUM BICMOS PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13239250
|
Filing Dt:
|
09/21/2011
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13241079
|
Filing Dt:
|
09/22/2011
|
Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
ESD PROTECTION STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13271120
|
Filing Dt:
|
10/11/2011
|
Publication #:
|
|
Pub Dt:
|
04/19/2012
| | | | |
Title:
|
LDMOS DEVICE STRUCTURE AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13271126
|
Filing Dt:
|
10/11/2011
|
Publication #:
|
|
Pub Dt:
|
04/19/2012
| | | | |
Title:
|
SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13276242
|
Filing Dt:
|
10/18/2011
|
Publication #:
|
|
Pub Dt:
|
04/19/2012
| | | | |
Title:
|
HIGH-VOLTAGE ESD PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13280226
|
Filing Dt:
|
10/24/2011
|
Publication #:
|
|
Pub Dt:
|
04/26/2012
| | | | |
Title:
|
SIGE HETEROJUNCTION BIPOLAR TRANSISTOR HAVING LOW COLLECTOR/BASE CAPACITANCE AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13288869
|
Filing Dt:
|
11/03/2011
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD OF SIGE EPITAXY WITH HIGH GERMANIUM CONCENTRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13315116
|
Filing Dt:
|
12/08/2011
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
PN-JUNCTION VARACTOR IN A BICMOS PROCESS AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13330458
|
Filing Dt:
|
12/19/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
VERTICAL PARASITIC PNP DEVICE IN A SILICON-GERMANIUM HBT PROCESS AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13338343
|
Filing Dt:
|
12/28/2011
|
Publication #:
|
|
Pub Dt:
|
04/19/2012
| | | | |
Title:
|
DECODING CIRCUIT WITHSTANDING HIGH VOLTAGE VIA LOW-VOLTAGE MOS TRANSISTOR AND THE IMPLEMENTING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13603658
|
Filing Dt:
|
09/05/2012
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
Title:
|
SUPERJUNCTION DEVICE AND METHOD FOR MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13608491
|
Filing Dt:
|
09/10/2012
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
SUPERJUNCTION STRUCTURE, SUPERJUNCTION MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13608545
|
Filing Dt:
|
09/10/2012
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
VERTICAL PNP DEVICE IN A SILICON-GERMANIUM BICMOS PROCESS AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13611441
|
Filing Dt:
|
09/12/2012
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
BOND PAD STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13613209
|
Filing Dt:
|
09/13/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
POLYSILICON-INSULATOR-SILICON CAPACITOR IN A SIGE HBT PROCESS AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13613236
|
Filing Dt:
|
09/13/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SIGE HBT AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13650192
|
Filing Dt:
|
10/12/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
METHOD OF INSERTING DUMMY PATTERNS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13658167
|
Filing Dt:
|
10/23/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13658927
|
Filing Dt:
|
10/24/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
SiGe HBT and Manufacturing Method Thereof
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13670871
|
Filing Dt:
|
11/07/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
STRUCTURE FOR PICKING UP A BURIED LAYER AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13671587
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SIGE HBT HAVING DEEP PSEUDO BURIED LAYER AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13671595
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SIGE HBT AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13671755
|
Filing Dt:
|
11/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
HIGH SPEED SIGE HBT AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13677577
|
Filing Dt:
|
11/15/2012
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
PARASITIC LATERAL PNP TRANSISTOR AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13680506
|
Filing Dt:
|
11/19/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
ULTRA HIGH VOLTAGE SIGE HBT AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13681889
|
Filing Dt:
|
11/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
METHOD OF MANUFACTURING NON-PHOTOSENSITIVE POLYIMIDE PASSIVATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13682123
|
Filing Dt:
|
11/20/2012
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13705437
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
METHOD OF FILLING SHALLOW TRENCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13712059
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
METHOD OF DOUBLE-SIDED PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13734464
|
Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
ZENER DIODE IN A SIGE BICMOS PROCESS AND METHOD OF FABRICATING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13753983
|
Filing Dt:
|
01/30/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
METHOD OF PREVENTING DOPANT FROM DIFFUSING INTO ATMOSPHERE IN A BICMOS PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13790292
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
FIELD STOP STRUCTURE, REVERSE CONDUCTING IGBT SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13836614
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
DIGITAL CORRECTION CIRCUIT FOR A PIPELINED ANALOG-TO-DIGITAL CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13888570
|
Filing Dt:
|
05/07/2013
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
SUPERJUNCTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13888596
|
Filing Dt:
|
05/07/2013
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
SIGE HBT DEVICE AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13899040
|
Filing Dt:
|
05/21/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
STRUCTURE FOR PICKING UP A COLLECTOR AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
13899858
|
Filing Dt:
|
05/22/2013
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
Title:
|
STRUCTURE FOR PICKING UP A COLLECTOR AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13911375
|
Filing Dt:
|
06/06/2013
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
Title:
|
ULTRA-HIGH VOLTAGE SIGE HBT DEVICE AND MANUFACTURING METHOD OF THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13947604
|
Filing Dt:
|
07/22/2013
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
Title:
|
LDMOS DEVICE WITH STEP-LIKE DRIFT REGION AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13956588
|
Filing Dt:
|
08/01/2013
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
Title:
|
RF LDMOS DEVICE AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13964678
|
Filing Dt:
|
08/12/2013
|
Publication #:
|
|
Pub Dt:
|
02/13/2014
| | | | |
Title:
|
RF LDMOS DEVICE AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13966847
|
Filing Dt:
|
08/14/2013
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
Title:
|
METHOD OF BACK-SIDE PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
13968515
|
Filing Dt:
|
08/16/2013
|
Publication #:
|
|
Pub Dt:
|
02/27/2014
| | | | |
Title:
|
METHOD OF FABRICATING P-TYPE SURFACE-CHANNEL LDMOS DEVICE WITH IMPROVED IN-PLANE UNIFORMITY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
13968687
|
Filing Dt:
|
08/16/2013
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2016
|
Application #:
|
13970050
|
Filing Dt:
|
08/19/2013
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
Title:
|
LDMOS DEVICE WITH STEP-LIKE DRIFT REGION AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
14019159
|
Filing Dt:
|
09/05/2013
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
SUPER-JUNCTION DEVICE AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14031684
|
Filing Dt:
|
09/19/2013
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
Title:
|
SILICON-BASED OPTICAL FIBER CLAMP AND METHODS OF FABRICATING THE SAME
|
|