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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036051/0786   Pages: 153
Recorded: 07/02/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 50
1
Patent #:
8358543
Issue Dt:
01/22/2013
Application #:
11229529
Filing Dt:
09/20/2005
Title:
Flash memory programming with data dependent control of source lines
2
Patent #:
8356361
Issue Dt:
01/15/2013
Application #:
11614309
Filing Dt:
12/21/2006
Publication #:
US20080109903
Pub Dt:
05/08/2008
Title:
SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
3
Patent #:
8367537
Issue Dt:
02/05/2013
Application #:
11801823
Filing Dt:
05/10/2007
Publication #:
US20080277712
Pub Dt:
11/13/2008
Title:
FLASH MEMORY CELL WITH A FLAIR GATE
4
Patent #:
8357965
Issue Dt:
01/22/2013
Application #:
12005869
Filing Dt:
12/28/2007
Publication #:
US20090020799
Pub Dt:
01/22/2009
Title:
SEMICONDUCTOR DEVICE HAVING MULTIPLE STORAGE REGIONS
5
Patent #:
8332572
Issue Dt:
12/11/2012
Application #:
12026299
Filing Dt:
02/05/2008
Publication #:
US20090198872
Pub Dt:
08/06/2009
Title:
WEAR LEVELING MECHANISM USING A DRAM BUFFER
6
Patent #:
8352671
Issue Dt:
01/08/2013
Application #:
12026302
Filing Dt:
02/05/2008
Publication #:
US20090198873
Pub Dt:
08/06/2009
Title:
PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
7
Patent #:
8359423
Issue Dt:
01/22/2013
Application #:
12048474
Filing Dt:
03/14/2008
Publication #:
US20090235012
Pub Dt:
09/17/2009
Title:
USING LPDDR1 BUS AS TRANSPORT LAYER TO COMMUNICATE TO FLASH
8
Patent #:
8370644
Issue Dt:
02/05/2013
Application #:
12129737
Filing Dt:
05/30/2008
Publication #:
US20090300312
Pub Dt:
12/03/2009
Title:
INSTANT HARDWARE ERASE FOR CONTENT RESET AND PSEUDO-RANDOM NUMBER GENERATION
9
Patent #:
8380917
Issue Dt:
02/19/2013
Application #:
12138307
Filing Dt:
06/12/2008
Publication #:
US20090150635
Pub Dt:
06/11/2009
Title:
COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE
10
Patent #:
8367466
Issue Dt:
02/05/2013
Application #:
12210113
Filing Dt:
09/12/2008
Publication #:
US20090230533
Pub Dt:
09/17/2009
Title:
MANUFACTURING STACKED SEMICONDUCTOR DEVICE
11
Patent #:
8391070
Issue Dt:
03/05/2013
Application #:
12326388
Filing Dt:
12/02/2008
Publication #:
US20100135082
Pub Dt:
06/03/2010
Title:
MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY
12
Patent #:
8352533
Issue Dt:
01/08/2013
Application #:
12332673
Filing Dt:
12/11/2008
Publication #:
US20090271461
Pub Dt:
10/29/2009
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT IN A CARRY COMPUTATION NETWORK HAVING A LOGIC BLOCKS WHICH ARE DYNAMICALLY RECONFIGURABLE
13
Patent #:
8386736
Issue Dt:
02/26/2013
Application #:
12337963
Filing Dt:
12/18/2008
Publication #:
US20100161935
Pub Dt:
06/24/2010
Title:
RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
14
Patent #:
8311054
Issue Dt:
11/13/2012
Application #:
12410086
Filing Dt:
03/24/2009
Publication #:
US20090213870
Pub Dt:
08/27/2009
Title:
TRANSMITTING/RECEIVING SYSTEM, NODE AND COMMUNICATION METHOD
15
Patent #:
8379443
Issue Dt:
02/19/2013
Application #:
12473037
Filing Dt:
05/27/2009
Publication #:
US20100302846
Pub Dt:
12/02/2010
Title:
IMPROVEMENT IN CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY
16
Patent #:
8314599
Issue Dt:
11/20/2012
Application #:
12479014
Filing Dt:
06/05/2009
Publication #:
US20090302817
Pub Dt:
12/10/2009
Title:
DC/DC CONVERTER CONTROL CIRCUIT AND DC/DC CONVERTER CONTROL METHOD
17
Patent #:
8324873
Issue Dt:
12/04/2012
Application #:
12636764
Filing Dt:
12/13/2009
Publication #:
US20100090673
Pub Dt:
04/15/2010
Title:
POWER SUPPLY APPARATUS AND POWER SUPPLY METHOD
18
Patent #:
8327052
Issue Dt:
12/04/2012
Application #:
12646291
Filing Dt:
12/23/2009
Publication #:
US20110153900
Pub Dt:
06/23/2011
Title:
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
19
Patent #:
8325531
Issue Dt:
12/04/2012
Application #:
12683732
Filing Dt:
01/07/2010
Publication #:
US20110164452
Pub Dt:
07/07/2011
Title:
MEMORY DEVICE
20
Patent #:
8375262
Issue Dt:
02/12/2013
Application #:
12690590
Filing Dt:
01/20/2010
Publication #:
US20110179319
Pub Dt:
07/21/2011
Title:
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
21
Patent #:
8319482
Issue Dt:
11/27/2012
Application #:
12716133
Filing Dt:
03/02/2010
Publication #:
US20100237841
Pub Dt:
09/23/2010
Title:
POWER SUPPLY AND POWER CONTROL DEVICE
22
Patent #:
8324716
Issue Dt:
12/04/2012
Application #:
12720547
Filing Dt:
03/09/2010
Publication #:
US20100164124
Pub Dt:
07/01/2010
Title:
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
23
Patent #:
8344711
Issue Dt:
01/01/2013
Application #:
12762668
Filing Dt:
04/19/2010
Publication #:
US20100283440
Pub Dt:
11/11/2010
Title:
POWER SUPPLY DEVICE, CONTROL CIRCUIT AND METHOD FOR CONTROLLING POWER SUPPLY DEVICE
24
Patent #:
8310008
Issue Dt:
11/13/2012
Application #:
12844392
Filing Dt:
07/27/2010
Publication #:
US20100289072
Pub Dt:
11/18/2010
Title:
ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES
25
Patent #:
8335110
Issue Dt:
12/18/2012
Application #:
12850470
Filing Dt:
08/04/2010
Publication #:
US20110032767
Pub Dt:
02/10/2011
Title:
SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY
26
Patent #:
8357563
Issue Dt:
01/22/2013
Application #:
12853856
Filing Dt:
08/10/2010
Publication #:
US20120038059
Pub Dt:
02/16/2012
Title:
STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK
27
Patent #:
8345503
Issue Dt:
01/01/2013
Application #:
12892251
Filing Dt:
09/28/2010
Publication #:
US20110075487
Pub Dt:
03/31/2011
Title:
BOOSTER CIRCUIT AND SEMICONDUCTOR MEMORY
28
Patent #:
8304914
Issue Dt:
11/06/2012
Application #:
12912602
Filing Dt:
10/26/2010
Publication #:
US20110156127
Pub Dt:
06/30/2011
Title:
FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF
29
Patent #:
8349685
Issue Dt:
01/08/2013
Application #:
12960437
Filing Dt:
12/03/2010
Publication #:
US20120142175
Pub Dt:
06/07/2012
Title:
DUAL SPACER FORMATION IN FLASH MEMORY
30
Patent #:
8354326
Issue Dt:
01/15/2013
Application #:
12961352
Filing Dt:
12/06/2010
Publication #:
US20110081767
Pub Dt:
04/07/2011
Title:
PRECISION TRENCH FORMATION THROUGH OXIDE REGION FORMATION FOR A SEMICONDUCTOR DEVICE
31
Patent #:
8314454
Issue Dt:
11/20/2012
Application #:
12970687
Filing Dt:
12/16/2010
Publication #:
US20110084330
Pub Dt:
04/14/2011
Title:
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
32
Patent #:
8345483
Issue Dt:
01/01/2013
Application #:
13011706
Filing Dt:
01/21/2011
Publication #:
US20120188820
Pub Dt:
07/26/2012
Title:
SYSTEM AND METHOD FOR ADDRESSING THRESHOLD VOLTAGE SHIFTS OF MEMORY CELLS IN AN ELECTRONIC PRODUCT
33
Patent #:
8385128
Issue Dt:
02/26/2013
Application #:
13020636
Filing Dt:
02/03/2011
Publication #:
US20110255347
Pub Dt:
10/20/2011
Title:
SEMICONDUCTOR MEMORY
34
Patent #:
8379464
Issue Dt:
02/19/2013
Application #:
13024979
Filing Dt:
02/10/2011
Publication #:
US20110242896
Pub Dt:
10/06/2011
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
35
Patent #:
8369161
Issue Dt:
02/05/2013
Application #:
13026075
Filing Dt:
02/11/2011
Publication #:
US20110141807
Pub Dt:
06/16/2011
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
36
Patent #:
8368577
Issue Dt:
02/05/2013
Application #:
13036429
Filing Dt:
02/28/2011
Publication #:
US20110234433
Pub Dt:
09/29/2011
Title:
A/D CONVERTER
37
Patent #:
8344510
Issue Dt:
01/01/2013
Application #:
13043383
Filing Dt:
03/08/2011
Publication #:
US20110156036
Pub Dt:
06/30/2011
Title:
SEMICONDUCTOR DEVICE WITH VOID DETECTION MONITOR
38
Patent #:
8389361
Issue Dt:
03/05/2013
Application #:
13069269
Filing Dt:
03/22/2011
Publication #:
US20110171819
Pub Dt:
07/14/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
39
Patent #:
8330209
Issue Dt:
12/11/2012
Application #:
13069710
Filing Dt:
03/23/2011
Publication #:
US20110169069
Pub Dt:
07/14/2011
Title:
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
40
Patent #:
8319273
Issue Dt:
11/27/2012
Application #:
13094744
Filing Dt:
04/26/2011
Publication #:
US20110198684
Pub Dt:
08/18/2011
Title:
SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
41
Patent #:
8329598
Issue Dt:
12/11/2012
Application #:
13153558
Filing Dt:
06/06/2011
Publication #:
US20110237060
Pub Dt:
09/29/2011
Title:
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
42
Patent #:
8379472
Issue Dt:
02/19/2013
Application #:
13155278
Filing Dt:
06/07/2011
Publication #:
US20110234856
Pub Dt:
09/29/2011
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
43
Patent #:
8318566
Issue Dt:
11/27/2012
Application #:
13156122
Filing Dt:
06/08/2011
Publication #:
US20110233651
Pub Dt:
09/29/2011
Title:
METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE
44
Patent #:
8309455
Issue Dt:
11/13/2012
Application #:
13165522
Filing Dt:
06/21/2011
Publication #:
US20110266609
Pub Dt:
11/03/2011
Title:
SIH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE
45
Patent #:
8325523
Issue Dt:
12/04/2012
Application #:
13195722
Filing Dt:
08/01/2011
Publication #:
US20110286273
Pub Dt:
11/24/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
46
Patent #:
8351268
Issue Dt:
01/08/2013
Application #:
13253634
Filing Dt:
10/05/2011
Publication #:
US20120069676
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
47
Patent #:
8339206
Issue Dt:
12/25/2012
Application #:
13310069
Filing Dt:
12/02/2011
Publication #:
US20120218049
Pub Dt:
08/30/2012
Title:
PLL
48
Patent #:
8361857
Issue Dt:
01/29/2013
Application #:
13323370
Filing Dt:
12/12/2011
Publication #:
US20120083096
Pub Dt:
04/05/2012
Title:
SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF
49
Patent #:
8384146
Issue Dt:
02/26/2013
Application #:
13428848
Filing Dt:
03/23/2012
Publication #:
US20120181601
Pub Dt:
07/19/2012
Title:
METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
50
Patent #:
8329530
Issue Dt:
12/11/2012
Application #:
13566741
Filing Dt:
08/03/2012
Publication #:
US20120302017
Pub Dt:
11/29/2012
Title:
METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE
Assignor
1
SPANSION, LLC
Exec Dt:
06/01/2015
Assignee
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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