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Reel/Frame:047841/0020   Pages: 13
Recorded: 12/21/2018
Attorney Dkt #:010829-9070.US03
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
08/11/2020
Application #:
16229257
Filing Dt:
12/21/2018
Publication #:
Pub Dt:
04/25/2019
Title:
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS
Assignors
1
Exec Dt:
08/20/2012
2
Exec Dt:
08/16/2012
3
Exec Dt:
08/16/2012
4
Exec Dt:
08/29/2012
5
Exec Dt:
08/20/2012
6
Exec Dt:
08/15/2012
7
Exec Dt:
08/22/2012
8
Exec Dt:
08/15/2012
9
Exec Dt:
08/15/2012
Assignee
1
8000 S. FEDERAL WAY
P.O. BOX 6
BOISE, IDAHO 83707-0006
Correspondence name and address
PERKINS COIE LLP - MICRON PATENT-SEA
PO BOX 1247
SEATTLE, WA 98111-1247

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