Total properties:
480
Page
1
of
5
Pages:
1 2 3 4 5
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2019
|
Application #:
|
15090305
|
Filing Dt:
|
04/04/2016
|
Publication #:
|
|
Pub Dt:
|
07/28/2016
| | | | |
Title:
|
METHODS AND DEVICES FOR PROGRAMMING A STATE MACHINE ENGINE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15674178
|
Filing Dt:
|
08/10/2017
|
Publication #:
|
|
Pub Dt:
|
02/14/2019
| | | | |
Title:
|
SHARED ADDRESS COUNTERS FOR MULTIPLE MODES OF OPERATION IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
15791886
|
Filing Dt:
|
10/24/2017
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
COMMAND SELECTION POLICY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15994815
|
Filing Dt:
|
05/31/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
THERMALLY OPTIMIZED PHASE CHANGE MEMORY CELLS AND METHODS OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
16019116
|
Filing Dt:
|
06/26/2018
|
Title:
|
WRITE LEVELING A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2020
|
Application #:
|
16028750
|
Filing Dt:
|
07/06/2018
|
Publication #:
|
|
Pub Dt:
|
11/07/2019
| | | | |
Title:
|
Securing Conditional Speculative Instruction Execution
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2022
|
Application #:
|
16028840
|
Filing Dt:
|
07/06/2018
|
Publication #:
|
|
Pub Dt:
|
11/07/2019
| | | | |
Title:
|
Static Identifications in Object-based Memory Access
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2019
|
Application #:
|
16031831
|
Filing Dt:
|
07/10/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
MEMORY DEVICE INCLUDING MULTIPLE SELECT LINES AND CONTROL LINES HAVING DIFFERENT VERTICAL SPACING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2020
|
Application #:
|
16032331
|
Filing Dt:
|
07/11/2018
|
Publication #:
|
|
Pub Dt:
|
01/16/2020
| | | | |
Title:
|
Predictive Paging to Accelerate Memory Access
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
16033076
|
Filing Dt:
|
07/11/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
APPARATUSES AND METHODS INCLUDING NESTED MODE REGISTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2020
|
Application #:
|
16035469
|
Filing Dt:
|
07/13/2018
|
Publication #:
|
|
Pub Dt:
|
01/16/2020
| | | | |
Title:
|
Isolated Performance Domains in a Memory System
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2021
|
Application #:
|
16036177
|
Filing Dt:
|
07/16/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
MEMORIES AND METHODS FOR PERFORMING VECTOR ATOMIC MEMORY OPERATIONS WITH MASK CONTROL AND VARIABLE DATA LENGTH AND DATA UNIT SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2020
|
Application #:
|
16036238
|
Filing Dt:
|
07/16/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
Methods Of Forming An Array Of Cross Point Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
16036549
|
Filing Dt:
|
07/16/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
MEMORY DEVICE INCLUDING MULTIPLE SELECT GATES AND DIFFERENT BIAS CONDITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2021
|
Application #:
|
16036578
|
Filing Dt:
|
07/16/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2020
|
Application #:
|
16036697
|
Filing Dt:
|
07/16/2018
|
Publication #:
|
|
Pub Dt:
|
01/16/2020
| | | | |
Title:
|
Electrically or Temperature Activated Shape-Memory Materials for Warpage Control
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
16037546
|
Filing Dt:
|
07/17/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PROVIDING CONSTANT DQS-DQ DELAY IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2020
|
Application #:
|
16038063
|
Filing Dt:
|
07/17/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
APPARATUSES AND METHODS FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2021
|
Application #:
|
16038108
|
Filing Dt:
|
07/17/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
MANAGING STORAGE PERFORMANCE CONSISTENCY WITH FEEDBACK CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2020
|
Application #:
|
16038387
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY CONDUCTIVE CONTACTS AND RELATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2020
|
Application #:
|
16038517
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
PROTOCOL INDEPENDENT TESTING OF MEMORY DEVICES USING A LOOPBACK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2021
|
Application #:
|
16038571
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
16038621
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2021
|
Application #:
|
16039236
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
NAND UNIT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2021
|
Application #:
|
16039269
|
Filing Dt:
|
07/18/2018
|
Publication #:
|
|
Pub Dt:
|
11/29/2018
| | | | |
Title:
|
NAND UNIT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
16039443
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2019
|
Application #:
|
16039559
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
MEMORIES HAVING SELECT DEVICES BETWEEN ACCESS LINES AND IN MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2020
|
Application #:
|
16039648
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
BIASED SAMPLING METHODOLOGY FOR WEAR LEVELING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
16039652
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/08/2018
| | | | |
Title:
|
METHODS OF FORMING AND OPERATING MICROELECTRONIC DEVICES INCLUDING DUMMY CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2020
|
Application #:
|
16039683
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
WRITE BUFFER MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2021
|
Application #:
|
16039707
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
16039769
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
16039995
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
COMMAND SIGNAL CLOCK GATING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2020
|
Application #:
|
16040337
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
Integrated Assemblies Which Include Non-Conductive-Semiconductor-Material and Conductive-Semiconductor-Material, and Methods of Forming Integrated Assemblies
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
16040382
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
USING A STATUS INDICATOR IN A MEMORY SUB-SYSTEM TO DETECT AN EVENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2020
|
Application #:
|
16040515
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
16040521
|
Filing Dt:
|
07/19/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
16040715
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
NON-VOLATILE MEMORY ADAPTED TO CONFIGURE LOW POWER DYNAMIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2020
|
Application #:
|
16041204
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
DIE-LEVEL ERROR RECOVERY SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2020
|
Application #:
|
16041374
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
Array Of Cross Point Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
16041388
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Methods Of Processing Silicon Nitride-Comprising Materials
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
16041455
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
16041480
|
Filing Dt:
|
07/20/2018
|
Title:
|
MEMORY DEVICE WITH A SIGNAL CONTROL MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
16041493
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
08/29/2019
| | | | |
Title:
|
MULTIPLE MEMORY TYPE MEMORY MODULE SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2021
|
Application #:
|
16041649
|
Filing Dt:
|
07/20/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
EXTENDED CROSS-TEMPERATURE HANDLING IN A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
16042255
|
Filing Dt:
|
07/23/2018
|
Publication #:
|
|
Pub Dt:
|
12/20/2018
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2022
|
Application #:
|
16042597
|
Filing Dt:
|
07/23/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
METHODS FOR EDGE TRIMMING OF SEMICONDUCTOR WAFERS AND RELATED APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2020
|
Application #:
|
16042812
|
Filing Dt:
|
07/23/2018
|
Publication #:
|
|
Pub Dt:
|
01/23/2020
| | | | |
Title:
|
HYBRID ITERATIVE ERROR CORRECTING AND REDUNDANCY DECODING OPERATIONS FOR MEMORY SUB-SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
16042924
|
Filing Dt:
|
07/23/2018
|
Title:
|
SYSTEMS AND METHODS FOR CONTROLLING DATA STROBE SIGNALS DURING READ OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2020
|
Application #:
|
16043049
|
Filing Dt:
|
07/23/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
MEMORY DEVICES WITH CONTROLLERS UNDER MEMORY PACKAGES AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
16043259
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
DETERMINING DATA STATES OF MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
16043350
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
03/14/2019
| | | | |
Title:
|
PHASE INTERPOLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
16043653
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
Apparatuses Having Memory Cells with Two Transistors and One Capacitor, and Having Body Regions of the Transistors Coupled with Reference Voltages
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2020
|
Application #:
|
16043869
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
Integrated Circuit, Construction Of Integrated Circuitry, And Method Of Forming An Array
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
16043893
|
Filing Dt:
|
07/24/2018
|
Title:
|
Integrated Circuitry Construction, A DRAM Construction, And A Method Used In Forming An Integrated Circuitry Construction
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
16043921
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2021
|
Application #:
|
16043959
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR DATA TRANSFER FROM SENSING CIRCUITRY TO A CONTROLLER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2019
|
Application #:
|
16044099
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
MEMORY APPARATUS WITH POST PACKAGE REPAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2020
|
Application #:
|
16044310
|
Filing Dt:
|
07/24/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
CELL PERFORMANCE RECOVERY USING CYCLING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2020
|
Application #:
|
16044703
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
Methods Used In Forming An Array Of Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2020
|
Application #:
|
16044887
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
Memory Circuitry Having A Pair Of Immediately-Adjacent Memory Arrays Having Space Laterally-There-Between That Has A Conductive Interconnect In The Space
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2021
|
Application #:
|
16045384
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
16045468
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
04/11/2019
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PARALLEL I/O OPERATIONS IN A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2019
|
Application #:
|
16045514
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
01/10/2019
| | | | |
Title:
|
REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2019
|
Application #:
|
16045516
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2019
|
Application #:
|
16045523
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
APPARATUSES AND METHODS OF READING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
16045526
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2021
|
Application #:
|
16045550
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2023
|
Application #:
|
16045562
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
Tunable integrated millimeter wave antenna using laser ablation and/or fuses
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
16045573
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
METHODS OF FORMING AN ARRAY OF CAPACITORS, METHODS OF FORMING AN ARRAY OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR, ARRAYS OF CAPACITORS, AND ARRAYS OF MEMORY CELLS INDIVIDUALLY COMPRISING A CAPACITOR AND A TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2020
|
Application #:
|
16045641
|
Filing Dt:
|
07/25/2018
|
Publication #:
|
|
Pub Dt:
|
08/08/2019
| | | | |
Title:
|
MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2019
|
Application #:
|
16046201
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
SYSTEMS AND METHODS FOR WAFER ALIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2019
|
Application #:
|
16046527
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR CHARGING A GLOBAL ACCESS LINE PRIOR TO ACCESSING A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2021
|
Application #:
|
16046686
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
16046767
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
HIGH VOLTAGE SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING ELECTRICAL CROSS-CONNECTIONS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
16046803
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
Integrated Assemblies Comprising Ferroelectric Transistors and Non-Ferroelectric Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
16046859
|
Filing Dt:
|
07/26/2018
|
Publication #:
|
|
Pub Dt:
|
11/15/2018
| | | | |
Title:
|
PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
16047949
|
Filing Dt:
|
07/27/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR CONVERTING A MASK TO AN INDEX
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
16047954
|
Filing Dt:
|
07/27/2018
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
Title:
|
METHODS FOR ON-DIE MEMORY TERMINATION AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2019
|
Application #:
|
16048037
|
Filing Dt:
|
07/27/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
APPARATUSES AND METHODS FOR FORMING DIE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2021
|
Application #:
|
16048075
|
Filing Dt:
|
07/27/2018
|
Publication #:
|
|
Pub Dt:
|
12/13/2018
| | | | |
Title:
|
WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CONFIGURATION MODES FOR BASEBAND UNITS AND REMOTE RADIO HEADS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2021
|
Application #:
|
16048078
|
Filing Dt:
|
07/27/2018
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
Title:
|
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2019
|
Application #:
|
16048506
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
BOOSTING CHANNELS OF MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
16048954
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
SCAN CHAIN OPERATION IN SENSING CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2021
|
Application #:
|
16049269
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
CONFIGURABLE LOGIC BLOCK NETWORKS AND MANAGING COHERENT MEMORY IN THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2022
|
Application #:
|
16049329
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
SELF-ASSEMBLED NANOSTRUCTURES INCLUDING METAL OXIDES AND SEMICONDUCTOR STRUCTURES COMPRISED THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2019
|
Application #:
|
16049411
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
Title:
|
SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2021
|
Application #:
|
16049439
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
01/30/2020
| | | | |
Title:
|
SELECTIVE BAD BLOCK UNTAG AND BAD BLOCK REUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2020
|
Application #:
|
16049576
|
Filing Dt:
|
07/30/2018
|
Publication #:
|
|
Pub Dt:
|
06/27/2019
| | | | |
Title:
|
MEMORY DEVICE WRITE CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2020
|
Application #:
|
16050141
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
Title:
|
Memory Cells and Arrays of Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2020
|
Application #:
|
16050501
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
08/29/2019
| | | | |
Title:
|
MEMORY MODULE DATA OBJECT PROCESSING SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2020
|
Application #:
|
16050585
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2020
|
Application #:
|
16050978
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
02/06/2020
| | | | |
Title:
|
Per Lane Duty Cycle Correction
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
16051117
|
Filing Dt:
|
07/31/2018
|
Title:
|
SYSTEMS AND METHODS FOR IMPROVING SIGNAL MARGIN FOR INPUT BUFFER CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
16051189
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
08/22/2019
| | | | |
Title:
|
DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2020
|
Application #:
|
16051202
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
08/22/2019
| | | | |
Title:
|
GAP DETECTION FOR CONSECUTIVE WRITE OPERATIONS OF A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
16051210
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
08/22/2019
| | | | |
Title:
|
WRITE LEVEL ARBITER CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
16051281
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
Title:
|
MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2021
|
Application #:
|
16051445
|
Filing Dt:
|
07/31/2018
|
Publication #:
|
|
Pub Dt:
|
02/06/2020
| | | | |
Title:
|
BANK AND CHANNEL STRUCTURE OF STACKED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
16051886
|
Filing Dt:
|
08/01/2018
|
Publication #:
|
|
Pub Dt:
|
12/06/2018
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND RELATED METHODS
|
|