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Reel/Frame:059410/0438   Pages: 127
Recorded: 03/16/2022
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1917
Page 3 of 20
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
Patent #:
6771543
Issue Dt:
08/03/2004
Application #:
10226912
Filing Dt:
08/22/2002
Publication #:
US20040037137
Pub Dt:
02/26/2004
Title:
PRECHARGING SCHEME FOR READING A MEMORY CELL
2
Patent #:
6784717
Issue Dt:
08/31/2004
Application #:
10229481
Filing Dt:
08/28/2002
Title:
INPUT BUFFER SYSTEM USING LOW VOLTAGE TRANSISTORS
3
Patent #:
6784700
Issue Dt:
08/31/2004
Application #:
10233696
Filing Dt:
09/03/2002
Title:
INPUT BUFFER CIRCUIT
4
Patent #:
6765271
Issue Dt:
07/20/2004
Application #:
10237805
Filing Dt:
09/10/2002
Publication #:
US20030008488
Pub Dt:
01/09/2003
Title:
METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
5
Patent #:
7761845
Issue Dt:
07/20/2010
Application #:
10238966
Filing Dt:
09/09/2002
Title:
METHOD FOR PARAMETERIZING A USER MODULE
6
Patent #:
6903002
Issue Dt:
06/07/2005
Application #:
10241236
Filing Dt:
09/11/2002
Title:
LOW-K DIELECTRIC LAYER WITH AIR GAPS
7
Patent #:
7142454
Issue Dt:
11/28/2006
Application #:
10243315
Filing Dt:
09/12/2002
Publication #:
US20040052111
Pub Dt:
03/18/2004
Title:
SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
8
Patent #:
6744666
Issue Dt:
06/01/2004
Application #:
10243792
Filing Dt:
09/12/2002
Title:
METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
9
Patent #:
6754106
Issue Dt:
06/22/2004
Application #:
10245146
Filing Dt:
09/16/2002
Title:
REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
10
Patent #:
7080222
Issue Dt:
07/18/2006
Application #:
10251623
Filing Dt:
09/20/2002
Title:
AUTOMATIC BACKUP AND RETRIEVAL OF DATA BETWEEN VOLATILE AND NON-VOLATILE MEMORIES
11
Patent #:
8533677
Issue Dt:
09/10/2013
Application #:
10256829
Filing Dt:
09/27/2002
Title:
GRAPHICAL USER INTERFACE FOR DYNAMICALLY RECONFIGURING A PROGRAMMABLE DEVICE
12
Patent #:
7194638
Issue Dt:
03/20/2007
Application #:
10260108
Filing Dt:
09/27/2002
Title:
DEVICE AND METHOD FOR MANAGING POWER CONSUMED BY A USB DEVICE
13
Patent #:
7439141
Issue Dt:
10/21/2008
Application #:
10277395
Filing Dt:
10/22/2002
Publication #:
US20030176043
Pub Dt:
09/18/2003
Title:
SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
14
Patent #:
6819185
Issue Dt:
11/16/2004
Application #:
10294808
Filing Dt:
11/13/2002
Title:
AMPLIFIER BIASING
15
Patent #:
7107036
Issue Dt:
09/12/2006
Application #:
10295662
Filing Dt:
11/15/2002
Title:
DEMODULATOR ARCHITECTURE AND ASSOCIATED METHODS
16
Patent #:
7159124
Issue Dt:
01/02/2007
Application #:
10298512
Filing Dt:
11/19/2002
Publication #:
US20030140206
Pub Dt:
07/24/2003
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY WITH A FUNCTION FOR PREVENTING UNAUTHORIZED READING
17
Patent #:
6946905
Issue Dt:
09/20/2005
Application #:
10301649
Filing Dt:
11/22/2002
Publication #:
US20030103029
Pub Dt:
06/05/2003
Title:
OFFSET CANCEL CIRCUIT OF VOLTAGE FOLLOWER EQUIPPED WITH OPERATIONAL AMPLIFIER
18
Patent #:
6768677
Issue Dt:
07/27/2004
Application #:
10302672
Filing Dt:
11/22/2002
Publication #:
US20040100824
Pub Dt:
05/27/2004
Title:
CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
19
Patent #:
7096340
Issue Dt:
08/22/2006
Application #:
10304389
Filing Dt:
11/25/2002
Title:
MEMORY MANAGEMENT
20
Patent #:
6911857
Issue Dt:
06/28/2005
Application #:
10305589
Filing Dt:
11/26/2002
Title:
CURRENT CONTROLLED DELAY CIRCUIT
21
Patent #:
7076703
Issue Dt:
07/11/2006
Application #:
10305700
Filing Dt:
11/26/2002
Title:
METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
22
Patent #:
6897110
Issue Dt:
05/24/2005
Application #:
10305750
Filing Dt:
11/26/2002
Title:
METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
23
Patent #:
6906959
Issue Dt:
06/14/2005
Application #:
10306252
Filing Dt:
11/27/2002
Publication #:
US20040169218
Pub Dt:
09/02/2004
Title:
METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
24
Patent #:
6743677
Issue Dt:
06/01/2004
Application #:
10306529
Filing Dt:
11/27/2002
Title:
METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
25
Patent #:
7074677
Issue Dt:
07/11/2006
Application #:
10307189
Filing Dt:
11/29/2002
Title:
MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
26
Patent #:
6795342
Issue Dt:
09/21/2004
Application #:
10307667
Filing Dt:
12/02/2002
Title:
SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
27
Patent #:
6731542
Issue Dt:
05/04/2004
Application #:
10313444
Filing Dt:
12/05/2002
Title:
CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
28
Patent #:
6737701
Issue Dt:
05/18/2004
Application #:
10313454
Filing Dt:
12/05/2002
Title:
STRUCTURE AND METHOD FOR REDUCING CHARGE LOSS IN A MEMORY CELL
29
Patent #:
6943126
Issue Dt:
09/13/2005
Application #:
10314381
Filing Dt:
12/06/2002
Title:
DEUTERIUM INCORPORATED NITRIDE
30
Patent #:
6828607
Issue Dt:
12/07/2004
Application #:
10315458
Filing Dt:
12/09/2002
Title:
DISCONTINUOUS NITRIDE STRUCTURE FOR NON-VOLATILE TRANSISTORS
31
Patent #:
7015135
Issue Dt:
03/21/2006
Application #:
10316569
Filing Dt:
12/10/2002
Publication #:
US20040110368
Pub Dt:
06/10/2004
Title:
METHOD AND SYSTEM FOR REDUCING CONTACT DEFECTS USING NON CONVENTIONAL CONTACT FORMATION METHOD FOR SEMICONDUCTOR CELLS
32
Patent #:
7342436
Issue Dt:
03/11/2008
Application #:
10316901
Filing Dt:
12/12/2002
Publication #:
US20030117209
Pub Dt:
06/26/2003
Title:
BIPOLAR SUPPLY VOLTAGE GENERATOR AND SEMICONDUCTOR DEVICE FOR SAME
33
Patent #:
6781465
Issue Dt:
08/24/2004
Application #:
10318543
Filing Dt:
12/13/2002
Title:
METHOD AND APPARATUS FOR DIFFERENTIAL SIGNAL DETECTION
34
Patent #:
7148739
Issue Dt:
12/12/2006
Application #:
10322491
Filing Dt:
12/19/2002
Publication #:
US20040119525
Pub Dt:
06/24/2004
Title:
CHARGE PUMP ELEMENT WITH BODY EFFECT CANCELLATION FOR EARLY CHARGE PUMP STAGES
35
Patent #:
7257147
Issue Dt:
08/14/2007
Application #:
10324990
Filing Dt:
12/20/2002
Title:
ENCODING VITERBI ERROR STATES INTO SINGLE CHIP SEQUENCES
36
Patent #:
7287112
Issue Dt:
10/23/2007
Application #:
10327207
Filing Dt:
12/20/2002
Title:
DYNAMIC RECONFIGURATION INTERRUPT SYSTEM AND METHOD
37
Patent #:
7180512
Issue Dt:
02/20/2007
Application #:
10335925
Filing Dt:
01/03/2003
Publication #:
US20030142053
Pub Dt:
07/31/2003
Title:
INTEGRATED CIRCUIT FREE FROM ACCUMULATION OF DUTY RATIO ERRORS
38
Patent #:
7151292
Issue Dt:
12/19/2006
Application #:
10342549
Filing Dt:
01/15/2003
Title:
DIELECTRIC MEMORY CELL STRUCTURE WITH COUNTER DOPED CHANNEL REGION
39
Patent #:
6894925
Issue Dt:
05/17/2005
Application #:
10342585
Filing Dt:
01/14/2003
Title:
FLASH MEMORY CELL PROGRAMMING METHOD AND SYSTEM
40
Patent #:
7064743
Issue Dt:
06/20/2006
Application #:
10352943
Filing Dt:
01/29/2003
Publication #:
US20030185425
Pub Dt:
10/02/2003
Title:
FINGER MOVEMENT DETECTION METHOD AND APPARATUS
41
Patent #:
6771545
Issue Dt:
08/03/2004
Application #:
10353558
Filing Dt:
01/29/2003
Title:
METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY
42
Patent #:
6842383
Issue Dt:
01/11/2005
Application #:
10354050
Filing Dt:
01/30/2003
Publication #:
US20040151034
Pub Dt:
08/05/2004
Title:
METHOD AND CIRCUIT FOR OPERATING A MEMORY CELL USING A SINGLE CHARGE PUMP
43
Patent #:
6967896
Issue Dt:
11/22/2005
Application #:
10354188
Filing Dt:
01/30/2003
Publication #:
US20040153620
Pub Dt:
08/05/2004
Title:
ADDRESS SCRAMBLE
44
Patent #:
7007134
Issue Dt:
02/28/2006
Application #:
10355177
Filing Dt:
01/31/2003
Publication #:
US20030167378
Pub Dt:
09/04/2003
Title:
MICROCOMPUTER, METHOD OF CONTROLLING CACHE MEMORY, AND METHOD OF CONTROLLING CLOCK
45
Patent #:
6639849
Issue Dt:
10/28/2003
Application #:
10356495
Filing Dt:
02/03/2003
Publication #:
US20030161188
Pub Dt:
08/28/2003
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROGRAMMING SECOND DYNAMIC REFERENCE CELL ACCORDING TO THRESHOLD VALUE OF FIRST DYNAMIC REFERENCE CELL
46
Patent #:
6765828
Issue Dt:
07/20/2004
Application #:
10356496
Filing Dt:
02/03/2003
Publication #:
US20030117841
Pub Dt:
06/26/2003
Title:
NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING OUT DATA
47
Patent #:
6888763
Issue Dt:
05/03/2005
Application #:
10358498
Filing Dt:
02/04/2003
Title:
COMPENSATED OSCILLATOR CIRCUIT FOR CHARGE PUMPS
48
Patent #:
6723638
Issue Dt:
04/20/2004
Application #:
10358866
Filing Dt:
02/05/2003
Title:
PERFORMANCE IN FLASH MEMORY DEVICES
49
Patent #:
6768679
Issue Dt:
07/27/2004
Application #:
10361378
Filing Dt:
02/10/2003
Title:
SELECTION CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
50
Patent #:
6674665
Issue Dt:
01/06/2004
Application #:
10368528
Filing Dt:
02/18/2003
Title:
SONOS LATCH AND APPLICATION
51
Patent #:
6870778
Issue Dt:
03/22/2005
Application #:
10373739
Filing Dt:
02/27/2003
Publication #:
US20030178643
Pub Dt:
09/25/2003
Title:
SEMICONDUCTOR DEVICE INCLUDING A VOLTAGE MONITORING CIRCUIT
52
Patent #:
6894473
Issue Dt:
05/17/2005
Application #:
10379744
Filing Dt:
03/05/2003
Title:
FAST BANDGAP REFERENCE CIRCUIT FOR USE IN A LOW POWER SUPPLY A/D BOOSTER
53
Patent #:
6781885
Issue Dt:
08/24/2004
Application #:
10379885
Filing Dt:
03/05/2003
Title:
METHOD OF PROGRAMMING A MEMORY CELL
54
Patent #:
6794764
Issue Dt:
09/21/2004
Application #:
10382726
Filing Dt:
03/05/2003
Publication #:
US20040173918
Pub Dt:
09/09/2004
Title:
CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE FORMATION
55
Patent #:
6744105
Issue Dt:
06/01/2004
Application #:
10382731
Filing Dt:
03/05/2003
Title:
MEMORY ARRAY HAVING SHALLOW BIT LINE WITH SILICIDE CONTACT PORTION AND METHOD OF FORMATION
56
Patent #:
6780708
Issue Dt:
08/24/2004
Application #:
10382744
Filing Dt:
03/05/2003
Title:
METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY
57
Patent #:
7028237
Issue Dt:
04/11/2006
Application #:
10385527
Filing Dt:
03/12/2003
Publication #:
US20040078672
Pub Dt:
04/22/2004
Title:
INTERNAL BUS TESTING DEVICE AND METHOD
58
Patent #:
6912160
Issue Dt:
06/28/2005
Application #:
10387064
Filing Dt:
03/11/2003
Publication #:
US20040179396
Pub Dt:
09/16/2004
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
59
Patent #:
7026687
Issue Dt:
04/11/2006
Application #:
10387427
Filing Dt:
03/14/2003
Publication #:
US20030197221
Pub Dt:
10/23/2003
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME
60
Patent #:
6744674
Issue Dt:
06/01/2004
Application #:
10387617
Filing Dt:
03/13/2003
Title:
CIRCUIT FOR FAST AND ACCURATE MEMORY READ OPERATIONS
61
Patent #:
6914824
Issue Dt:
07/05/2005
Application #:
10392912
Filing Dt:
03/21/2003
Publication #:
US20030179628
Pub Dt:
09/25/2003
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY THAT IS BASED ON A VIRTUAL GROUND METHOD
62
Patent #:
6975541
Issue Dt:
12/13/2005
Application #:
10394254
Filing Dt:
03/24/2003
Publication #:
US20040190341
Pub Dt:
09/30/2004
Title:
ALTERNATING APPLICATION OF PULSES ON TWO SIDES OF A CELL
63
Patent #:
6885244
Issue Dt:
04/26/2005
Application #:
10394255
Filing Dt:
03/24/2003
Publication #:
US20040189385
Pub Dt:
09/30/2004
Title:
OPERATIONAL AMPLIFIER WITH FAST RISE TIME
64
Patent #:
6667212
Issue Dt:
12/23/2003
Application #:
10394565
Filing Dt:
03/21/2003
Title:
ALIGNMENT SYSTEM FOR PLANAR CHARGE TRAPPING DIELECTRIC MEMORY CELL LITHOGRAPHY
65
Patent #:
8049539
Issue Dt:
11/01/2011
Application #:
10401604
Filing Dt:
03/31/2003
Publication #:
US20030184352
Pub Dt:
10/02/2003
Title:
CIRCUIT WITH VARIATION CORRECTION FUNCTION
66
Patent #:
6885955
Issue Dt:
04/26/2005
Application #:
10402774
Filing Dt:
03/28/2003
Title:
SEMICONDUCTOR PROCESS YIELD ANALYSIS BASED ON EVALUATION OF PARAMETRIC RELATIONSHIP
67
Patent #:
6717839
Issue Dt:
04/06/2004
Application #:
10404941
Filing Dt:
03/31/2003
Title:
BIT-LINE SHIELDING METHOD FOR FERROELECTRIC MEMORIES
68
Patent #:
6798275
Issue Dt:
09/28/2004
Application #:
10406415
Filing Dt:
04/03/2003
Publication #:
US20040196093
Pub Dt:
10/07/2004
Title:
FAST, ACCURATE AND LOW POWER SUPPLY VOLTAGE BOOSTER USING A/D CONVERTER
69
Patent #:
6956768
Issue Dt:
10/18/2005
Application #:
10413800
Filing Dt:
04/15/2003
Publication #:
US20040208057
Pub Dt:
10/21/2004
Title:
METHOD OF PROGRAMMING DUAL CELL MEMORY DEVICE TO STORE MULTIPLE DATA STATES PER CELL
70
Patent #:
6768157
Issue Dt:
07/27/2004
Application #:
10413829
Filing Dt:
04/15/2003
Publication #:
US20030178667
Pub Dt:
09/25/2003
Title:
MEMORY DEVICE
71
Patent #:
6822909
Issue Dt:
11/23/2004
Application #:
10422090
Filing Dt:
04/24/2003
Title:
METHOD OF CONTROLLING PROGRAM THRESHOLD VOLTAGE DISTRIBUTION OF A DUAL CELL MEMORY DEVICE
72
Patent #:
6778442
Issue Dt:
08/17/2004
Application #:
10422092
Filing Dt:
04/24/2003
Title:
METHOD OF DUAL CELL MEMORY DEVICE OPERATION FOR IMPROVED END-OF-LIFE READ MARGIN
73
Patent #:
6861696
Issue Dt:
03/01/2005
Application #:
10429140
Filing Dt:
05/03/2003
Title:
STRUCTURE AND METHOD FOR A TWO-BIT MEMORY CELL
74
Patent #:
6773990
Issue Dt:
08/10/2004
Application #:
10429150
Filing Dt:
05/03/2003
Title:
METHOD FOR REDUCING SHORT CHANNEL EFFECTS IN MEMORY CELLS AND RELATED STRUCTURE
75
Patent #:
6944057
Issue Dt:
09/13/2005
Application #:
10431065
Filing Dt:
05/06/2003
Title:
METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
76
Patent #:
6791880
Issue Dt:
09/14/2004
Application #:
10431320
Filing Dt:
05/06/2003
Title:
NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
77
Patent #:
7232729
Issue Dt:
06/19/2007
Application #:
10431321
Filing Dt:
05/06/2003
Title:
A METHOD FOR MANUFACTURING A DOUBLE BITLINE IMPLANT
78
Patent #:
6917068
Issue Dt:
07/12/2005
Application #:
10454517
Filing Dt:
06/05/2003
Title:
SEMICONDUTOR DEVICE HAVING CONDUCTIVE STRUCTURES FORMED NEAR A GATE ELECTRODE
79
Patent #:
6788580
Issue Dt:
09/07/2004
Application #:
10454630
Filing Dt:
06/05/2003
Publication #:
US20030206435
Pub Dt:
11/06/2003
Title:
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA ERASING METHOD
80
Patent #:
7064983
Issue Dt:
06/20/2006
Application #:
10454820
Filing Dt:
06/05/2003
Publication #:
US20040081010
Pub Dt:
04/29/2004
Title:
METHOD FOR PROGRAMMING A REFERENCE CELL
81
Patent #:
6839279
Issue Dt:
01/04/2005
Application #:
10455310
Filing Dt:
06/06/2003
Publication #:
US20040246784
Pub Dt:
12/09/2004
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
82
Patent #:
6765254
Issue Dt:
07/20/2004
Application #:
10460279
Filing Dt:
06/12/2003
Title:
STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE AND INCREASING DATA RETENTION IN MEMORY CELLS
83
Patent #:
6906966
Issue Dt:
06/14/2005
Application #:
10461437
Filing Dt:
06/16/2003
Publication #:
US20040252555
Pub Dt:
12/16/2004
Title:
FAST DISCHARGE FOR PROGRAM AND VERIFICATION
84
Patent #:
7652930
Issue Dt:
01/26/2010
Application #:
10537857
Filing Dt:
06/07/2005
Publication #:
US20060056240
Pub Dt:
03/16/2006
Title:
METHOD, CIRCUIT AND SYSTEM FOR ERASING ONE OR MORE NON-VOLATILE MEMORY CELLS
85
Patent #:
7324374
Issue Dt:
01/29/2008
Application #:
10600065
Filing Dt:
06/20/2003
Publication #:
US20040257873
Pub Dt:
12/23/2004
Title:
MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
86
Patent #:
6957297
Issue Dt:
10/18/2005
Application #:
10603136
Filing Dt:
06/23/2003
Title:
SIMULTANEOUS EXECUTION COMMAND MODES IN A FLASH MEMORY DEVICE
87
Patent #:
8530977
Issue Dt:
09/10/2013
Application #:
10609159
Filing Dt:
06/27/2003
Title:
APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT
88
Patent #:
7023046
Issue Dt:
04/04/2006
Application #:
10617450
Filing Dt:
07/11/2003
Publication #:
US20050006693
Pub Dt:
01/13/2005
Title:
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Issue Dt:
02/13/2007
Application #:
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Filing Dt:
07/23/2003
Publication #:
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Pub Dt:
07/01/2004
Title:
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90
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Issue Dt:
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Application #:
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Filing Dt:
07/24/2003
Publication #:
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Pub Dt:
06/24/2004
Title:
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Patent #:
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Issue Dt:
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Application #:
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Filing Dt:
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Publication #:
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Pub Dt:
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Title:
NONVOLATILE MEMORY HAVING A TRAP LAYER
92
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Issue Dt:
06/13/2006
Application #:
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Filing Dt:
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Publication #:
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Pub Dt:
03/18/2004
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF BLOCKS AND A SENSING CIRCUIT PROVIDED IN EACH OF THE BLOCKS FOR COMPARING DATA WITH A REFERENCE SIGNAL HAVING A LOAD IMPOSED THEREON
93
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Issue Dt:
06/13/2006
Application #:
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Filing Dt:
08/06/2003
Title:
MEMORY DEVICE AND METHOD OF SIMULTANEOUS FABRICATION OF CORE AND PERIPHERY OF SAME
94
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Issue Dt:
01/17/2006
Application #:
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Filing Dt:
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Title:
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95
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Issue Dt:
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Application #:
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Filing Dt:
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Title:
MEMORY CIRCUIT FOR PROVIDING WORD LINE REDUNDANCY IN A MEMORY SECTOR
96
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Issue Dt:
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Filing Dt:
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Title:
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Title:
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Title:
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100
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Issue Dt:
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Application #:
10654739
Filing Dt:
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Title:
PATTERNING FOR ELONGATED VSS CONTACT ON FLASH MEMORY
Assignor
1
MUFG UNION BANK, N.A.
Exec Dt:
04/16/2020
Assignees
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
2
SPANSION LLC
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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